1. Determine the CPI on the pipelined MIC-3 processor for the MULT instruction implemented by the microcode presented in class (it will be posted on the course web page). What instruction will need to be modified for the MIC-3 implementation?

2. (See problem CA7-4 for reference) Modify the MIC-1 architecture to be able to handle interrupts. You may assume a single-level/single-priority scheme which makes the least demands on the microprogram level. Assume also that the vector to the entry point of the interrupt handler in the operating system is in memory location 0, and that all interrupt servicing is handled at that level. Introduce a new ISA level instruction to allow interrupt masking and resetting by the handler program. Describe the changed hardware and the changes to the microprogram that are required.