Andrew Cassidy

Department of Electrical and Computer Engineering
The Johns Hopkins University

acassidy [at] jhu [dot] edu

I received my Ph.D. from the Johns Hopkins University in Electrical and Computer Engineering in December 2010. Following graduation, we packed up the family and headed to sunny California, where I now work at IBM Research Almaden, in the cognitive computing group.


Research

My research focuses on two key research areas:
  1. Single Chip Parallel Computing (Chip-Multiprocessor architecture and optimization)
  2. Neural and Cognitive Computing

Most recently, I have been investigating objective functions for optimizing Chip-Multiprocessors (CMPs). As integrated circuit technology steadily progresses, the capability to build chip-multiprocessors (CMPs) with hundreds or thousands of processor cores is imminent. This prospect poses daunting hurdles for the electronic design automation (EDA) industry. Current design methodologies, such as instruction set simulators (ISS) and cycle accurate simulators, are too detailed to quickly explore the system-level design space. Instead, we present an objective function that balances the performance gains of parallelism with the costs and benefits of other architectural elements, namely processor microarchitecture, memory hierarchy, and communication bandwidth in a global optimization process.

Prior research investigated the cortex as a massively parallel computational architecture. In the cortex, the canonical computational unit is the neuron. Although there is some diversification within types of neurons, all cortical computations seem to be carried out by the single canonical computational unit, the neuron. The breadth of cortical computations is enormous, from sensory processing tasks such as vision and speech processing, to cognitive tasks such as analysis, mathematics, logic, and conciousness, to creative tasks of art, music, and composition. Remarkably, all of these cortical computations are performed with the same computational construct, the neuron, using different parameterizations and interconnection schemes. What is it about the neuron that makes it such a versatile and powerful computational unit? How are the higher-level computations (or algorithms) constructed from this fundamental unit?



Research affliations while at JHU:



Publications: Chip-Multiprocessor Architectural Optimization

Andrew S. Cassidy and Andreas G. Andreou, "Beyond Amdahl's Law: An objective function that links multiprocessor performance gains to delay and energy," IEEE Transactions on Computers (accepted for publication July 2011).

Andrew Cassidy, Kai Yu, Haolang Zhou, and Andreas G. Andreou, "A high-level analytical model for application specific CMP design exploration." Design and Test, Europe (DATE), Grenoble, France, March, 2011.

Andrew Cassidy and Andreas G. Andreou. "Analytical Methods for the Design and Optimization of Single Chip-Multiprocessor Architectures." IEEE Conference on Information Sciences and Systems (CISS), Baltimore, 2009

JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy. "High-level Modeling and Simulation of Single-Chip Programmable Heterogeneous Multiprocessors," ACM Transactions on the Design Automation of Electronic Systems, Vol. 10, pp. 431-461, July 2005.

Andrew S. Cassidy, JoAnn M. Paul, and Donald E. Thomas, "Layered, Multi-Threaded, High-Level Performance Design," Design and Test, Europe (DATE), March, 2003.

Andrew S. Cassidy, "High-Level Performance Modeling and Design Exploration," MS Project, Electrical and Computer Engineering Department, CMU, October 2002, CSSI Tech Report 02-38.

JoAnn Paul, Christopher Andrews, Andrew Cassidy, Donald Thomas, "System-Level Modeling of a Network Switch SoC," International Symposium on System Synthesis (ISSS) 2002.


Publications: Neural and Cognitive Computing

(as well as sensory information processing)


Andrew Cassidy and Andreas G. Andreou. "Design of a one million neuron single FPGA neuromorphic system for real-time multimodal scene analysis." IEEE Conference on Information Sciences and Systems (CISS), Baltimore, March 2011.
Note: this paper also bridges the gap between these two research topics, applying analytical chip-multiprocessor models to neural computing.

Cassidy, Andrew; Andreou, Andreas G.; Georgiou, Julius; "A combinational digital logic approach to STDP." IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15-18 May 2011.

Cassidy, Andrew; Murray, Thomas; Andreou, Andreas G.; Georgiou, Julius; "Evaluating on-chip interconnects for low operating frequency silicon neuron arrays." IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15-18 May 2011.

Georgiou, J.; Pouliquen, P.; Cassidy, A.; Garreau, G.; Andreou, C.; Stuarts, G.; d'Urbal, C.; Andreou, A.G.; Denham, S.; Wennekers, T.; Mill, R.; Winkler, I.; Bohm, T.; Szalardy, O.; Klump, G.M.; Jones, S.; Bendixen, A.; "A multimodal-corpus data collection system for cognitive acoustic scene analysis." IEEE Conference on Information Sciences and Systems (CISS), Baltimore, 2011

Pouliquen, P.O.; Cassidy, A.; Andreou, A.G.; Garreau, G.; Georgiou, J.; "A wireless architecture for distributed sensing/actuation and pre-processing with microsecond synchronization." IEEE Conference on Information Sciences and Systems (CISS), Baltimore, 2011

W. Spiegl, G. Stemmer, E. Lasarcyk, V. Kolhatkar, A. Cassidy, B. Potard, S. Shum, Y. Chol Song, P. Xu, P. Beyerlein, J. Harnsberger, E. Noeth. "Analyzing Features for Automatic Age Estimation on Cross-Sectional Data." Interspeech, Brighton 2009.

F. Folowosele, T.J. Hamilton, A. Harrison, S. Mihalas, E. Niebur, A. Cassidy, A. Andreou, R. Etienne-Cummings. "A Switched Capacitor Implementation of the Generalized Linear Integrate-And-Fire Neuron." IEEE International Symposium on Circuits and Systems (ISCAS), Taiwan 2009.

Andrew Cassidy and Andreas G. Andreou. "Dynamical Digital Silicon Neurons." IEEE International Workshop on Biomedical Circuits and Systems (BioCAS), Baltimore, Nov 2008.

Andrew Cassidy, Zhaonian Zhang, and Andreas G. Andreou. "Neuromorphic Interconnects Using Ultra Wideband Radio." IEEE International Workshop on Biomedical Circuits and Systems (BioCAS), Baltimore, Nov 2008.

Andrew Cassidy, Zhaonian Zhang, and Andreas G. Andreou. "Impulse Radio Address Event Interconnects for Body Area Networks and Neural Prostheses." Argentine Conference on Micro-Nanoelectronics, Technology and Applications, CAMTA. pp.87-92, 18-19 Sept. 2008.

Andrew Cassidy, Susan Denham, Patrick Kanold, and Andreas G. Andreou. "FPGA Based Silicon Spiking Neural Array." IEEE International Workshop on Biomedical Circuits and Systems (BioCAS), Montreal, Nov 2007.

Andrew Cassidy and Ralph Etienne-Cummings. "Non-Linear Neural Spike Train Decoding Via Polynomial Kernel Regression." 29th IEEE EMBS Annual International Conference, August 23-26, 2007, Lyon, France.

Andrew Cassidy and Virantha Ekanayake. "A Biologically Inspired Tactile Sensor Array Utilizing Phase-Based Computation." IEEE International Workshop on Biomedical Circuits and Systems (BioCAS), London, Dec 2006.

Edward Lin, Andy Cassidy, Dan Hook, Avinash Baliga, Tsuhan Chen, "Hand Tracking using Spatial Gesture Modeling and Visual Feedback for a Virtual DJ System," 4th IEEE International Conference on Multimodal Interfaces (ICMI) 2002.


Patents

Helmsen, Eric J.; Cassidy, Andrew; Chandrasekhara, Arati; and George, Edwin, to Ericsson AB "Filtering for timing distribution system in networking products" U.S. Patent No. 07245685 Cl. 375-371.


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