Office: Barton Hall 404

Telephone: (410) 516-7380

E-Mail: robert.jenkins@jhuapl.edu

A study of the structure and organization of classical von Neuman uniprocessor computers. Topics include: a brief history of modern machines starting from the Turing computer model, instruction sets, addressing, RISC versus CISC, traps and interrupt handling, twos complement arithmetic, adders and ALUs, CSA's, Booth's algorithm, multiplication and division, control unit design, micro-programming, dynamic versus static linking, memory systems and the memory hierarchy, paging, segmentation, cache hardware, cache organizations, and replacement policies.

• D. Patterson and C. Sequin, "A VLSI RISC", IEEE Computer, 1983.
• D. Fairclough et al, "A Unique Microprocessor Instruction Set", IEEE Micro, 1982.
• R. Colwell et al, "Computers, Complexity, and Controversy", IEEE Computer, 1986.
• J. Hennessy, "VLSI RISC Processors", VLSI Systems Design, 1985.
• Smith, "Cache Memory Design: an Evolving Art", IEEE Spectrum, 1989.

This is a lecture course, whose overall objective is to provide students with a thorough grounding in the architecture of classical von Neuman computers. The emphasis is on modern methods, however one objective is knowledge of the historical roots and evolution of these methods, and why things evolved as they did. The material is limited to non-parallel processing with the exception of instruction pipelining in RISC machines. (Considerations of pipelining, ILP, and multiprocessors is deferred to the follow-on course, ECE 520.426, Parallel Processing Architectures.)

A second objective is to create an understanding of the tradeoffs involved in computer design, along with an understanding of the methods used to evaluate performance and obtain the data needed for trade studies. The tradeoff and boundary between hardware and software is explicitly examined. The material is slanted toward hardware, and an objective is an understanding of how computer features and CPU control are implemented via finite state logic, buses, EPROM, and registers.

Another objective is to give design experience through problems requiring architectural decisions. The course stresses the hierarchical model of a computer system and the hierarchical approach to managing complexity in systems design. A final explicit goal, and not the least, is to prepare the students to be able to read and understand the current literature in computer architecture. This goal is considered of major importance for such a constantly evolving subject.

Two 2.5 hour Exams, Midterm and Final, each worth 100 points toward final grade.

Approx. 11 homework assignments, each worth 4 points if turned in. Weekly homework assignments are due the following week, and will be gone over in class. Homework will be accepted 1 week late if a student misses class for a valid reason.

There may be an in-class or take-home problem that will be worth 30 points.

Students must do the homework assignments themselves, as the problems are important to learning the course material, and are similar to the problems on the exams.

The Johns Hopkins University Undergraduate and Graduate Programs Catalogue, 1998-1999, pp. 31, 32, 40.

The Johns Hopkins University Undergraduate Advising Manual, Fall 1998, pp. 36, 37.

CA = Computer Architecture, notes by Jenkins et al

SCO = Structured Computer Organization, by Tanenbaum

2. Note for problem CA3-2: In proving redundancy by showing an equivalent sequence of instructions, remember that you must only use instructions from the residual language set. You can't use an instruction in a replacement sequence if it is targeted for later elimination.

4.  Expansion of problem CA4-1: In addition to working CA4-1, as a second part of problem, think about how to somehow quantify the basis for the decision about how many stack items to offload into memory on a HW stack overflow. You might consider, for example, the two cases where there are 15 straight PUSHes immediately after the overflow versus15 alternating PUSH/POP's. Try to quantify these cases assuming that the stack holds 10 items, each micro-operation (such as load a register from another register, or shift the stack) takes one clock, and that a memory read or write takes 8 clocks.

5. Comments on SCO-Chap. 3: We will review some of the material on digital circuits in class, but it is mainly assumed you are familiar with this. Also, we will cover only a limited discussion of buses in class, however you should read the material in sections 3.4-3.7 to at least become familiar with the PCI bus and the Universal Serial bus, used extensively in current generation desktop PC's. To understand the internal workings of the CPU at the micro-program level, I believe it helps to work with a simple structure, so the details don't begin to obscure the central ideas. Consequently, in the course we will focus only on a very simple model of asynchronous buses internal to the CPU and with a single, external memory data bus. You should, however, understand the difference between an asynchronous and a synchronous bus. Although most modern computers look more akin to SCO-figure 3.34, we will ignore any issues associated with bus bridging and bus arbitration. This is not to say these are not important areas, and it is only in the interests of time that we reduce this coverage. There is always a new synchronous bus on the horizon, and it is hard to keep up with the details. However, if you understand the basic principles, you can always learn the details of this or that specific bus if you need to use it in a design.

520.422 - Things You Should Know for the Final